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PE43713 product specification ultracmos? rf digital step attenuator, 9 khzC6 ghz ?2015, peregrine semiconductor corporation. all rights reserved. ? headquarters: 9380 carroll park drive, san diego, ca, 92121 product specification doc-49614-1 C (3/2015) www.psemi.com features ? flexible attenuation steps of 0.25 db, 0.5 db and 1 db up to 31.75 db ? glitch-less attenuation state transitions ? monotonicity: 0.25 db up to 4 ghz, 0.5 db up to 5 ghz and 1 db up to 6 ghz ? extended +105 c operating temperature ? parallel and serial programming interfaces with serial addressability ? packaging?32-lead 5 5 mm qfn applications ? test and measurement (t&m) ? general purpose rf attenuator product description the PE43713 is a 50 ? , harp? technology-enhanced, 7-bit rf digital step attenuator (dsa) that supports a broad frequency range from 9 khz to 6 ghz. it features glitch-less attenuation state transitions, supports 1.8v control voltage and includes an extended operating temperature range to +105 c and optional v ss_ext bypass mode to improve spurious performance, making th is device ideal for test and measurement (t&m). the PE43713 is a pin-compatible upgraded version of the pe43703. an integrated digital control interface supports both serial addressable and parallel programmi ng of the attenuation, including the capability to program an initial attenuation state at power-up. the PE43713 covers a 31.75 db attenuation range in 0.25 db, 0.5 db and 1db steps. it is capable of maintaining 0.25 db monotonicity through 4 ghz, 0.50 db monoton icity through 5 ghz and 1 db monotonicity through 6 ghz. in addition, no external blocking capacitors are required if 0 vdc is present on the rf ports. the PE43713 is manufactured on peregrine?s ultracmos ? process, a patented variation of silicon-on-insulator (soi) technology on a sapphire substrate. figure 1 ? PE43713 functional diagram 7 rf input rf output control logic interface switched attenuator array v ss_ext p/s a0 a1 a2 parallel control serial in clk (optional) le
PE43713 ultracmos? rf digital step attenuator page 2 doc-49614-1 C (3/2015) www.psemi.com peregrine?s harp technology enhancements deliver high linearity and excellent harmonics performance. it is an innovative feature of the ultracmos process, offe ring the performance of gaas with the economy and integration of conventional cmos. optional external v ss control for proper operation, the v ss_ext control pin must be grounded or tied to the v ss voltage specified in table 2 . when the v ss_ext control pin is grounded, fets in the switch are biased with an internal negative voltage generator. for applications that require the lowest possible spur performance, v ss_ext can be applied externally to bypass the internal negative voltage generator. absolute maximum ratings exceeding absolute maximum ratings listed in table 1 may cause permanent damage. operation should be restricted to the limits in table 2 . operation between operating range maximum and absolute maximum for extended periods may reduce reliability. esd precautions when handling this ultracmos device, observe the same precautions as with any other esd-sensitive devices. although this device contains circuitry to protect it fr om damage due to esd, precautions should be taken to avoid exceeding the rating specified in table 1 . latch-up immunity unlike conventional cmos devices, ultracmos devices are immune to latch-up. table 1 ? absolute maximum ratings for PE43713 parameter/condition min max unit supply voltage, v dd ?0.3 5.5 v digital input voltage ?0.3 3.6 v rf input power, 50 ? 9 khz?48 mhz >48 mhz?6 ghz figure 5 +31 dbm dbm storage temperature range ?65 +150 c esd voltage hbm, all pins (1) 3000 v esd voltage cdm, all pins (2) 1000 v notes: 1) human body model (mil?std 883 method 3015). 2) charged device model (jedec jesd22?c101).
PE43713 ultracmos? rf digital step attenuator doc-49614-1 C (3/2015) page 3 www.psemi.com recommended operating conditions table 2 lists the recommending operating condition for th e PE43713. devices should not be operated outside the recommended operating conditions listed below. table 2 ? recommended operating condition for PE43713 parameter min typ max unit normal mode, v ss_ext = 0v (1) supply voltage, v dd 2.3 5.5 v supply current, i dd 150 200 a bypass mode, v ss_ext = ?3.4v (2) supply voltage, v dd (v dd 3.4v see table 3 for full spec compliance) 2.7 3.4 5.5 v supply current, i dd 50 80 a negative supply voltage, v ss_ext ?3.6 ?2.4 v negative supply current, i ss ?40 ?16 a normal or bypass mode digital input high 1.17 3.6 v digital input low ?0.3 0.6 v digital input current 17.5 a rf input power, cw (3) 9 khz?48 mhz >48 mhz?6 ghz figure 5 +23 dbm dbm rf input power, pulsed (4) 9 khz?48 mhz >48 mhz?6 ghz figure 5 +28 dbm dbm operating temperature range ?40 +25 +105 c notes: 1) normal mode: connect v ss_ext (pin 20) to gnd (v ss_ext = 0v) to enable internal negative voltage generator. 2) bypass mode: use v ss_ext (pin 20) to bypass and disable internal negative voltage generator. 3) 100% duty cycle, all bands, 50 ? . 4) pulsed, 5% duty cycle of 4620 s period, 50 ? .
PE43713 ultracmos? rf digital step attenuator page 4 doc-49614-1 C (3/2015) www.psemi.com electrical specifications table 3 provides the PE43713 key electrical specifications at 25 c, rf1 = rf in , rf2 = rf out (z s = z l = 50 ? ), unless otherwise specified. normal mode (1) is at v dd = 3.3v and v ss_ext = 0v. bypass mode (2) is at v dd = 3.4v and v ss_ext = ?3.4v. table 3 ? PE43713 electrical specifications parameter condition frequency min typ max unit operating frequency 9 khz 6 ghz as shown attenuation range 0.25 db step 0.5 db step 1 db step 0?31.75 0?31.50 0?31.00 db db db insertion loss 9 khz?1.0 ghz 1.0?2.2 ghz 2.2?4.0 ghz 4.0?6.0 ghz 1.3 1.6 1.95 2.45 1.5 1.85 2.4 2.8 db db db db attenuation error 0.25 db step 0?8 db 9 khz?2.2 ghz (0.20 + 1.5% of attenuation setting) db 8.25?31.75 db 9 khz?2.2 ghz (0.20 + 2.0% of attenuation setting) db 0?31.75 db >2.2?3.0 ghz (0.15 + 3.0% of attenuation setting) db 0?31.75 db >3.0?4.0 ghz (0.25 + 3.5% of attenuation setting) db 0.5 db step 0?8 db 9 khz?2.2 ghz (0.20 + 1.5% of attenuation setting) db 8.5?31.5 db 9 khz?2.2 ghz (0.20 + 2.0% of attenuation setting) db 0?31.5 db >2.2?3.0 ghz (0.15 + 3.0% of attenuation setting) db 0?31.5 db >3.0?5.0 ghz (0.25 + 5.0% of attenuation setting) db
PE43713 ultracmos? rf digital step attenuator doc-49614-1 C (3/2015) page 5 www.psemi.com attenuation error 1 db step 0?8 db 9 khz?2.2 ghz (0.20 + 1.5% of attenuation setting) db 9?31 db 9 khz?2.2 ghz (0.20 + 2.0% of attenuation setting) db 0?31 db >2.2?3.0 ghz (0.15 + 3.0% of attenuation setting) db 0?31 db >3.0?5.0 ghz (0.25 + 5.0% of attenuation setting) db 0?31 db >5.0?6.0 ghz (0.25 + 5.0% of attenuation setting) db return loss input port or output port 9 khz?4 ghz 4?6 ghz 13 15 db db relative phase all states 9 khz?4 ghz 4?6 ghz 27 42 deg deg input 0.1db compression point (3) 48 mhz?6 ghz 31 dbm input ip3 two tones at +18 dbm, 20 mhz spacing 4 ghz 6 ghz 57 56 dbm dbm rf t rise /t fall 10%/90% rf 200 ns settling time rf settled to within 0.05 db of final value 1.6 s switching time 50% ctrl to 90% or 10% rf 275 ns attenuation transient (envelope) 2 ghz 0.3 db notes: 1) normal mode: connect v ss_ext (pin 20) to gnd (v ss_ext = 0v) to enable internal negative voltage generator. 2) bypass mode: use v ss_ext (pin 20) to bypass and disable internal negative voltage generator. 3) the input 0.1 db compression point is a linearity figure of merit. refer to table 2 for the operating rf input power (50 ? ). table 3 ? PE43713 electrical specifications (cont.) parameter condition frequency min typ max unit
PE43713 ultracmos? rf digital step attenuator page 6 doc-49614-1 C (3/2015) www.psemi.com switching frequency the PE43713 has a maximum 25 khz switching rate in normal mode (pin 20 tied to ground). a faster switching rate is available in bypass mode (pin 20 tied to v ss_ext ). the rate at which the PE43713 can be switched is then limited to the switching time as specified in table 3 . switching frequency is defined to be the speed at which the dsa can be toggled across attenuation states. switching time is the time duration between the point the control signal reaches 50% of the final value and the point the output signal reaches within 10% or 90% of its target value. spur-free performance the typical spurious performance of the PE43713 in normal mode is ?130 dbm (pin 20 tied to ground). if spur-free performance is desired, the internal negative voltage generator can be disabled by applying a negative voltage to v ss_ext (pin 20). glitch-less attenuation state transitions the PE43713 features a novel architecture to provide the best-in-class glitch-less transition behavior when changing attenuation states. when rf input power is applied, the output power spikes are greatly reduced ( 0.3 db) during attenuation state changes when comparing to previous generations of dsas. truth tables table 4 ? table 6 provide the truth tables for the PE43713. table 4 ? parallel truth table parallel control setting attenuation setting rf1?rf2 d6 d5 d4 d3 d2 d1 d0 l l l l l l l reference il l l l l l l h 0.25 db l l l l l h l 0.5 db llllhll 1 db lllhlll 2 db llhllll 4 db lhlllll 8 db h l l l l l l 16 db hhhhhhh 31.75 db table 5 ? serial address word truth table address word address setting a7 (msb) a6 a5 a4 a3 a2 a1 a0 x x x x x l l l 000 x x x x x l l h 001 x x x x x l h l 010 xxxxxlhh 011 x x x x x h l l 100 x x x x x h l h 101 xxxxxhhl 110 x xxxxhhh 111 table 6 ? serial attenuation word truth table attenuation word attenuation setting rf1?rf2 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) lllllll l reference il lllllll h 0.25 db llllllh l 0.5 db lllllhl l 1 db llllhll l 2 db lllhlll l 4 db llhllll l 8 db lhlllll l 16 db l h h h h h h h 31.75 db table 4 ? parallel truth table (cont.) parallel control setting attenuation setting rf1?rf2 d6 d5 d4 d3 d2 d1 d0
PE43713 ultracmos? rf digital step attenuator doc-49614-1 C (3/2015) page 7 www.psemi.com serial addressable register map figure 2 provides the serial addressable register map for the PE43713. figure 2 ? serial addressable register map attenuation word lsb (first in) msb (last in) q7 q6 q5 q4 q3 q2 q1 q0 d7 d6 d5 d4 d3 d2 d1 d0 q15 q14 q13 q12 q11 q10 q9 q8 a6 a7 a5 a4 a3 a2 a1 a0 address word d7 must be set to logic low bits can either be set to logic high or logic low 4 18.25 = 73 73 01001001 a ddress word: xxxxx011 a ttenuation word: 01001001 serial input: xxxxx01101001001 for example, to program the 18.25 db state at address 3: the attenuation word is derived directly from the value of the attenuation state. to find the attenuation word, multiply the value of the state by four, then convert to binary.
PE43713 ultracmos? rf digital step attenuator page 8 doc-49614-1 C (3/2015) www.psemi.com programming options parallel/serial selection either a parallel or serial addressable interface can be used to control the PE43713. the p /s bit provides this selection, with p /s = low selecting the parallel interface and p /s = high selecting the serial interface. parallel mode interface the parallel interface consists of seven cmos- compatible control lines that select the desired attenu- ation state, as shown in table 4 . the parallel interface timing requirements are defined by figure 4 (parallel interface timing diagram), table 9 (parallel and direct interface ac character- istics) and switching time ( table 3 ). for latched parallel programming, the latch enable (le) should be held low while changing attenuation state control values then pulse le high to low (per figure 4 ) to latch new attenuation state into the device. for direct parallel programming, the le line should be pulled high. changing attenuation state control values will change device state to new attenuation. direct mode is ideal for manual control of the device (using hardwire, switches, or jumpers). serial-addressable interface the serial-addressable interface is a 16-bit serial-in, parallel-out shift register buffered by a transparent latch. the 16-bits make up two words comprised of 8- bits each. the first word is the attenuation word, which controls the state of the dsa. the second word is the address word, which is compared to the static (or programmed) logical states of the a0, a1 and a2 digital inputs. if there is an address match, the dsa changes state; otherwise its current state will remain unchanged. figure 3 illustrates an example timing diagram for programming a state. it is required that all parallel control inputs be grounded when the dsa is used in serial-addressable mode. the serial-addressable interface is controlled using three cmos-compatible signals: si, clock (clk) and le. the si and clk inputs allow data to be serially entered into the shift register. serial data is clocked in lsb first. the shift register must be loaded while le is held low to prevent the attenuator value from changing as data is entered. the le input should then be toggled high and brought low again, latching the new data into the dsa. the address word truth table is listed in table 5 . the attenuation word truth table is listed in table 6 . a programming example of the serial register is illustrated in figure 2 . the serial timing diagram is illustrated in figure 3 . power-up control settings the PE43713 will always initialize to the maximum attenuation setting (31.75 db) on power-up for both the serial addressable and latched parallel modes of operation and will remain in this setting until the user latches in the next programming word. in direct parallel mode, the dsa can be preset to any state within the 31.75 db range by pre-setting the parallel control pins prior to power-up. in this mode, there is a 400 s delay between the time the dsa is powered- up to the time the desired state is set. during this power-up delay, the device attenuates to the maximum attenuation setting (31.75 db) before defaulting to the user defined state. if the control pins are left floating in this mode during power-up, the device will default to the minimum attenuation setting (insertion loss state). dynamic operation between serial and parallel programming modes is possible. if the dsa powers up in serial mode (p /s = high), all the parallel control inputs di[6:0] must be set to logic low. prior to toggling to parallel mode, the dsa must be programmed serially to ensure d[7] is set to logic low. if the dsa powers up in either latched or direct parallel mode, all parallel pins di[6:0] must be set to logic low prior to toggling to serial addressable mode (p /s = high), and held low until the dsa has been programmed serially to ensure bit d[7] is set to logic low. the sequencing is only required once on power-up. once completed, the dsa may be toggled between serial and parallel programming modes at will.
PE43713 ultracmos? rf digital step attenuator doc-49614-1 C (3/2015) page 9 www.psemi.com figure 3 ? serial timing diagram di[6:0] do[6:0] si clk t disu t pssu t sisu t sih bits can either be set to logic high or logic low d[7] must be set to logic low t clkl t clkh t lepw t lesu t psih t dih t pd valid le p/s d[0] d[1] d[2] d[3] d[4] d[5] d[6] d[7] figure 4 ? latched parallel/direct parallel timing diagram t lepw t dih t disu t dipd t psih t pd valid valid di[6:0] do[6:0] le p/s t pssu table 7 ? latch and clock specifications latch enable shift clock function 0 shift register clocked x contents of shift register transferred to attenuator core
PE43713 ultracmos? rf digital step attenuator page 10 doc-49614-1 C (3/2015) www.psemi.com table 8 ? serial interface ac characteristics (*) parameter/condition min max unit serial clock frequency, f clk 10 mhz serial clock high time, t clkh 30 ns serial clock low time, t clkl 30 ns last serial clock rising edge setup time to latch enable rising edge, t lesu 10 ns latch enable minimum pulse width, t lepw 30 ns serial data setup time, t sisu 10 ns serial data hold time, t sih 10 ns parallel data setup time, t disu 100 ns parallel data hold time, t dih 100 ns address setup time, t asu 100 ns address hold time, t ah 100 ns parallel/serial setup time, t pssu 100 ns parallel/serial hold time, t psih 100 ns digital register delay (internal), t pd 10 ns note: * v dd = 3.3v or 5.0v, ?40 c, < t a < +105 c, unless otherwise specified. table 9 ? parallel and direct interface ac characteristics (*) parameter/condition min max unit latch enable minimum pulse width, t lepw 30 ns parallel data setup time, t disu 100 ns parallel data hold time, t dih 100 ns parallel/serial setup time, t pssu 100 ns parallel/serial hold time, t psih 100 ns digital register delay (internal), t pd 10 ns digital register delay (internal, direct mode only), t dipd 5n s note: * v dd = 3.3v or 5.0v, ?40 c < t a < +105 c, unless otherwise specified.
PE43713 ultracmos? rf digital step attenuator doc-49614-1 C (3/2015) page 11 www.psemi.com figure 5 ? power de-rating curve, 9 khzC6 ghz, C40 to +105 c ambient, 50 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 0.01 0.05 0.50 5.00 50.00 500.00 5000.00 maximum rf input power (dbm) frequency (mhz) p0.1 db compression ( 48 mhz) pulsed ( 48 mhz) cw & pulsed (< 48 mhz) cw ( 48 mhz)
PE43713 ultracmos? rf digital step attenuator page 12 doc-49614-1 C (3/2015) www.psemi.com typical performance data figure 6 ? figure 32 show the typical performance data at 25 c and v dd = 3.3v, rf1 = rf in , rf2 = rf out (z s = z l = 50 ? ) unless otherwise specified. figure 6 ? insertion loss vs temperature -6 -5 -4 -3 -2 -1 0 0123456 insertion loss (db) frequency (ghz) -40c 25c 85c 105c
PE43713 ultracmos? rf digital step attenuator doc-49614-1 C (3/2015) page 13 www.psemi.com figure 7 ? input return loss vs attenuation setting -45 -40 -35 -30 -25 -20 -15 -10 -5 0 0123456 return loss (db) frequency (ghz) 0 db 0.25 db 0.5 db 1 db 2 db 4 db 8 db 16 db 28 db 31.75 db figure 8 ? output return loss vs attenuation setting -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 0123456 return loss (db) frequency (ghz) 0 db 0.25 db 0.5 db 1 db 2 db 4 db 8 db 16 db 28 db 31.75 db
PE43713 ultracmos? rf digital step attenuator page 14 doc-49614-1 C (3/2015) www.psemi.com figure 9 ? input return loss for 16 db attenuation setting vs temperature figure 10 ? output return loss for 16 db attenuation setting vs temperature -40 -35 -30 -25 -20 -15 -10 -5 0 0123456 return loss (db) frequency (ghz) -40c 25c 85c 105c -25 -20 -15 -10 -5 0 0123456 return loss (db) frequency (ghz) -40c 25c 85c 105c
PE43713 ultracmos? rf digital step attenuator doc-49614-1 C (3/2015) page 15 www.psemi.com figure 11 ? relative phase error vs attenuation setting figure 12 ? relative phase error for 31.75 db attenuation setting vs frequency -10 0 10 20 30 40 50 60 0123456 relative phase error (deg) frequency (ghz) 0 db 0.25 db 0.5 db 1 db 2 db 4 db 8 db 16 db 31.75 db 0 10 20 30 40 50 60 -40 25 85 105 relative phase error (deg) temperature (c) 0.9 ghz 1.8 ghz 2.2 ghz 3 ghz 4 ghz 5 ghz 6 ghz
PE43713 ultracmos? rf digital step attenuator page 16 doc-49614-1 C (3/2015) www.psemi.com figure 13 ? attenuation error @ 900 mhz vs temperature figure 14 ? attenuation error @ 1800 mhz vs temperature -0.25 0 0.25 0.5 0.75 0 4 8 12 16 20 24 28 32 attenuation error (db) attenuation setting (db) -40c 25c 85c 105c -0.25 0 0.25 0.5 0.75 0 4 8 12 16 20 24 28 32 attenuation error (db) attenuation setting (db) -40c 25c 85c 105c
PE43713 ultracmos? rf digital step attenuator doc-49614-1 C (3/2015) page 17 www.psemi.com figure 15 ? attenuation error @ 2200 mhz vs temperature figure 16 ? attenuation error @ 3000 mhz vs temperature -0.25 0 0.25 0.5 0.75 0 4 8 12 16 20 24 28 32 attenuation error (db) attenuation setting (db) -40c 25c 85c 105c -0.25 0 0.25 0.5 0.75 0 4 8 12 16 20 24 28 32 attenuation error (db) attenuation setting (db) -40c 25c 85c 105c
PE43713 ultracmos? rf digital step attenuator page 18 doc-49614-1 C (3/2015) www.psemi.com figure 17 ? attenuation error @ 4000 mhz vs temperature figure 18 ? iip3 vs attenuation setting 0 0.25 0.5 0.75 1 0 4 8 121620242832 attenuation error (db) attenuation setting (db) -40c 25c 85c 105c 50 55 60 65 70 3456 input ip3 (dbm) frequency (ghz) 0 db 3.5 db 7.5 db 11 db 14 db 17.5 db 21.5 db 24.75 db 28 db 31.75 db
PE43713 ultracmos? rf digital step attenuator doc-49614-1 C (3/2015) page 19 www.psemi.com figure 19 ? 0.25 db step attenuation vs frequency (*) note: * monotonicity is held so long as step attenuation does not cross below ?0.25 db. figure 20 ? 0.25 db step, actual vs frequency -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 4 8 12 16 20 24 28 32 step attenuation (db) attenuation setting (db) 1 ghz 2.2 ghz 3 ghz 4 ghz 0 5 10 15 20 25 30 35 0 4 8 121620242832 actual attenuation (db) ideal attenuation (db) 1 ghz 2.2 ghz 3 ghz 4 ghz
PE43713 ultracmos? rf digital step attenuator page 20 doc-49614-1 C (3/2015) www.psemi.com figure 21 ? 0.25 db major state bit error vs attenuation setting figure 22 ? 0.25 db attenuation error vs frequency -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 01234 attenuation error (db) frequency (ghz) 0.25 db 0.5 db 1 db 2 db 4 db 8 db 16 db 31.75 db -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 4 8 121620242832 attenuation error (db) attenuation setting (db) 1 ghz 2.2 ghz 3 ghz 4 ghz
PE43713 ultracmos? rf digital step attenuator doc-49614-1 C (3/2015) page 21 www.psemi.com figure 23 ? 0.5 db step attenuation vs frequency (*) note: * monotonicity is held so long as step attenuation does not cross below ?0.5 db. figure 24 ? 0.5 db step, actual vs frequency -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 4 8 12 16 20 24 28 32 step attenuation (db) attenuation setting (db) 1 ghz 2.2 ghz 3 ghz 4 ghz 5 ghz 0 5 10 15 20 25 30 35 0 4 8 121620242832 actual attenuation (db) ideal attenuation (db) 1 ghz 2.2 ghz 3 ghz 4 ghz 5 ghz
PE43713 ultracmos? rf digital step attenuator page 22 doc-49614-1 C (3/2015) www.psemi.com figure 25 ? 0.5 db major state bit error vs attenuation setting figure 26 ? 0.5 db attenuation error vs frequency -0.2 0 0.2 0.4 0.6 0.8 1 1.2 012345 attenuation error (db) frequency (ghz) 0.5 db 1 db 2 db 4 db 8 db 16 db 31.5 db -0.2 0 0.2 0.4 0.6 0.8 1 1.2 0 4 8 121620242832 attenuation error (db) attenuation setting (db) 1 ghz 2.2 ghz 3 ghz 4 ghz 5 ghz
PE43713 ultracmos? rf digital step attenuator doc-49614-1 C (3/2015) page 23 www.psemi.com figure 27 ? 1 db step attenuation vs frequency (*) note: * monotonicity is held so long as step attenuation does not cross below ?1 db. figure 28 ? 1 db step, actual vs frequency -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0 4 8 121620242832 step attenuation (db) attenuation setting (db) 1 ghz 2.2 ghz 3 ghz 4 ghz 5 ghz 6 ghz 0 5 10 15 20 25 30 35 0 4 8 121620242832 actual attenuation (db) ideal attenuation (db) 1 ghz 2.2 ghz 3 ghz 4 ghz 5 ghz 6 ghz
PE43713 ultracmos? rf digital step attenuator page 24 doc-49614-1 C (3/2015) www.psemi.com figure 29 ? 1 db major state bit error vs attenuation setting figure 30 ? 1 db attenuation error vs frequency -0.2 0 0.2 0.4 0.6 0.8 1 1.2 0123456 attenuation error (db) frequency (ghz) 1 db 2 db 4 db 8 db 16 db 31 db -0.2 0 0.2 0.4 0.6 0.8 1 1.2 0 4 8 12 16 20 24 28 32 attenuation error (db) attenuation setting (db) 1 ghz 2.2 ghz 3 ghz 4 ghz 5 ghz 6 ghz
PE43713 ultracmos? rf digital step attenuator doc-49614-1 C (3/2015) page 25 www.psemi.com figure 31 ? attenuation transient (15.75C16 db), typical switching time = 275 ns figure 32 ? attenuation transient (16C15.75 db), typical switching time = 275 ns -17.0 -16.8 -16.6 -16.4 -16.2 -16.0 -15.8 -15.6 -15.4 0 400 800 1200 1600 2000 2400 2800 3200 envelope power (dbm) time (ns) power (dbm) trigger starts ~730 ns glitch = 0.15 db -17.0 -16.8 -16.6 -16.4 -16.2 -16.0 -15.8 -15.6 -15.4 0 400 800 1200 1600 2000 2400 2800 3200 envelope power (dbm) time (ns) power (dbm) trigger starts ~730 ns glitch = 0.03 db
PE43713 ultracmos? rf digital step attenuator page 26 doc-49614-1 C (3/2015) www.psemi.com evaluation kit the digital step attenuator evaluation board (evb) was designed to ease customer evaluation of the PE43713 digital step attenuator. the PE43713 evb supports direct parallel, latched parallel and serial modes. evaluation kit setup connect the evb with the usb dongle board and usb cable as shown in figure 33 . direct parallel programming procedure direct parallel programming is suitable for manual operation without software programming. for manual direct parallel programming, position the parallel/ serial (p/s) select switch to the parallel position. the le switch must be switched to high position. switches d0?d6 are sp3t switches that enable the user to manually program the parallel bits. when d0? d6 are toggled to the high position, logic high is presented to the parallel input. when toggled to the low position, logic low is presented to the parallel input. setting le and d0?d6 to the ext position presents as open, which is set for software programming of latched parallel and serial modes. table 4 depicts the parallel truth table. latched parallel programming procedure for automated latched parallel programming, connect the usb dongle board and cable that is provided with the evaluation kit (evk) from the usb port of the pc to the j5 header of the PE43713 evb, and set the le and d0?d6 sp3t switches to the ext position. position the parallel/serial (p/s) select switch to the parallel position. the evaluation software is written to operate the dsa in parallel mode. ensure that the software gui is set to latched parallel mode. use the software gui to enable the desired attenuation state. the software gui automati- cally programs the dsa each time an attenuation state is enabled. serial addressable pr ogramming procedure for automated serial programming, connect the usb dongle board and cable that is provided with the evk from the usb port of the pc to the j5 header of the PE43713 evb, and set the le and d0?d6 sp3t switches to the ext position. position the parallel/ serial (p/s) select switch to the serial position. prior to programming, the user must define an address setting using the hdr2 header pin. jump the middle column of pins on the hdr2 header (a0?a2) to the left column of pins to set logic low, or jump the middle row of pins to the right column of pins to set logic high. if the hdr2 pins are left open, then 000 becomes the default address. the software gui is written to operate the dsa in serial mode. use the software gui to enable each setting to the desired attenuation state. the software gui automatically programs the dsa each time an attenuation state is enabled. figure 33 ? evaluation kit for PE43713
PE43713 ultracmos? rf digital step attenuator doc-49614-1 C (3/2015) page 27 www.psemi.com figure 34 ? evaluation kit layout for PE43713
PE43713 ultracmos? rf digital step attenuator page 28 doc-49614-1 C (3/2015) www.psemi.com pin information this section provides pinout information for the PE43713. figure 35 shows the pin map of this device for the available package. table 10 provides a description for each pin. figure 35 ? pin configuration (top view) exposed ground pad clk c8 c16 si gnd gnd gnd c2 c1 c0.5 c0.25 gnd gnd gnd a1 a2 v ss_ext gnd rf2 gnd gnd le gnd p/s a0 gnd gnd rf1 gnd v dd 1 3 4 5 6 7 8 2 9 11 12 13 14 15 16 10 32 30 29 28 27 26 25 31 24 22 21 20 19 18 17 23 c4 gnd pin 1 dot marking table 10 ? pin descriptions for PE43713 pin no. pin name description 1, 5, 6, 8?17, 19 gnd ground 2 v dd supply voltage 3p /s serial/parallel mode select 4 a0 address bit a0 connection 7 rf1 (1) rf1 port (rf input) 18 rf2 (1) rf2 port (rf output) 20 v ss_ext (2) external v ss negative voltage con- trol 21 a2 address bit a2 connection 22 a1 address bit a1 connection 23 le serial interface latch enable input 24 clk serial interface clock input 25 si serial interface data input 26 c16 (d6) (3) parallel control bit, 16 db 27 c8 (d5) (3) parallel control bit, 8 db 28 c4 (d4) (3) parallel control bit, 4 db 29 c2 (d3) (3) parallel control bit, 2 db 30 c1 (d2) (3) parallel control bit, 1 db 31 c0.5 (d1) (3) parallel control bit, 0.5 db 32 c0.25 (d0) (3) parallel control bit, 0.25 db pad gnd exposed pad: ground for proper operation notes: 1) rf pins 7 and 18 must be at 0 vdc. the rf pins do not require dc blocking capacitors for proper operation if the 0 vdc requirement is met. 2) use v ss_ext (pin 20) to bypass and disable internal negative voltage generator. connect v ss_ext (pin 20) to gnd (v ss_ext = 0v) to enable internal negative voltage generator. 3) ground c0.25, c0.5, c1, c2, c4, c8 and c16 if not in use.
PE43713 ultracmos? rf digital step attenuator doc-49614-1 C (3/2015) page 29 www.psemi.com packaging information this section provides packaging data including the moisture sensitivity level, package drawing, package marking and tape-and-reel information. moisture sensitivity level the moisture sensitivity level rating for the PE43713 in the 32-lead 5 5 mm qfn package is msl1. package drawing top-marking specification figure 36 ? package mechanical drawing for 32-lead 5 5? 0.85 mm qfn figure 37 ? package marking specifications for PE43713 top view bottom view side view recommended land pattern a 0.10 c (2x) c 0.10 c 0.05 c seating plane b 0.10 c (2x) 0.10 c a b 0.05 c all features pin #1 corner 5.00 5.00 0.400.05 (x32) 3.100.05 0.250.05 (x32) 0.50 3.50 ref 3.100.05 0.850.05 0.05 ref 0.203 ref (x28) chamfer 0.35 x 45 0.30 (x32) 0.60 (x32) 3.15 3.15 5.40 5.40 0.50 (x28) 1 8 9 32 17 24 25 16 = yy = ww = zzzzzzz = pin 1 indicator last two digits of assembly year assembly work week assembly lot code (maximum seven characters) 43713 yyww zzzzzzz
PE43713 ultracmos? rf digital step attenuator page 30 doc-49614-1 C (3/2015) www.psemi.com tape and reel specification PE43713 figure 38 ? tape and reel specifications for 32-lead 5 5? 0.85 mm qfn device orientation in tape pin 1 t k0 a0 b0 p0 p1 d1 a section a-a a direction of feed d0 e w0 p2 see note 3 see note 1 f see note 3 a0 b0 k0 d0 d1 e f p0 p1 p2 t w0 5.25 5.25 1.10 1.50 + 0.1/ -0.0 1.5 min 1.75 0.10 5.50 0.05 4.00 8.00 2.00 0.05 0.30 0.05 12.00 0.30 notes: 1. 10 sprocket hole pitch cumulative tolerance 0.2 2. camber in compliance with eia 481 3. pocket position relative to sprocket hole measured as true position of pocket, not pocket hole dimensions are in millimeters unless otherwise specified
PE43713 product specification www.psemi.com doc-49614-1 C (3/2015) document categories advance information the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification the datasheet contains final data. in the event peregrine decides to change the specifications, peregri ne will notify customers of the intended changes by issuing a cnf (customer notification form). not recommended for new designs (nrnd) this product is in production but is not recommended for new designs. end of life (eol) this product is currently going th rough the eol process. it has a specific last-time buy date. obsolete this product is discontinued. orde rs are no longer accepted for this product. sales contact for additional information, contact sales at sales@psemi.com. disclaimers the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this infor mation. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or grante d to any third party. peregrine?s products are not designed or intended for use in devi ces or systems intended for surgical implant, or in other appl ications intended to support or sustain life, or in any applicati on in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, incl uding consequential or incidental damages, aris ing out of the use of its products in such applications. patent statement peregrine products are protected under one or more of the following u.s. patents: patents.psemi.com copyright and trademark ?2015, peregrine semiconductor corporation. all rights reserved. the peregrine name, l ogo, utsi and ultracmo s are registered tr ademarks and harp, multiswitch and dune are trademar ks of peregrine semiconductor corp. ordering information table 11 lists the available ordering codes for the PE43713 as well as available shipping methods. table 11 ? order codes for PE43713 order codes description packaging shipping method PE43713a-z PE43713 digital step attenuator green 32-lead 5 5 mm qfn 3000 units / t&r ek43713-02 PE43713 evaluation kit evaluation kit 1 / box

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